Last week a group of 19 European electronics businesses and academics got behind a $half-billion pilot-line project which hopes to industrialise FD-SOI technology. I’ll cover that in a moment, but if you find physics challenging, please take a deep breath before reading on. It’s one of five pilot-line initiatives that have come about because the European Commission is taking a real interest in the role Europe plays in various micro- and nano-electronic components and systems.
The Commission issued a communication earlier in May outlining some of the reasons it sees these as being so important. I’ve read it and it didn’t tell me that much new to be honest but it did have some good sound-bites. “Reverse the decline of EU’s share of world’s supply”, and “Seize opportunities arising from non-conventional fields” and, probably most significantly “The impact of micro- and nano- electronics on the whole economy is estimated as 10% of worldwide GDP”… that’s a lot of zeros. So I thought I’d summarise what one of these fields, fully depleted silicon-on-insulator (FD-SOI) is, and why it’s been seemingly picked as one of five areas for European excellence.
FD-SOI is sometimes called extremely thin silicon-on-insulator (ET-SOI) and is an alternative to the bulk silicon used for building CMOS devices today. Transistors built on FD-SOI have a very shallow channel, which improves the gate’s ability to remove carriers from that channel when the device needs to be switched off. This means that the off-leakage current, which plagues all current semiconductor designs to some degree and mobile devices more than most, can be substantially reduced. This off-leakage current issue becomes increasingly worse as chip designs become physically smaller and more densely integrated to cut costs and ironically reduce energy drain.
The way FD-SOI transistors are constructed is different to the bulk CMOS silicon used in current devices. An extra oxide layer simplifies the make-up of the channel (the core of the transistor) making it easier to manufacture, and that’s where the fully-depleted term comes from. The extra layer gives the transistor two effective gates that can operate at different voltages. This double-gate structure theoretically means that transistors can be operated in varying states of speed-and-efficiency and these can be dynamically adjusted while operating. There are disadvantages obviously, not least the additional complexity of operation, and anything that moves advanced semiconductor designs away from ‘industry standard’ processes, where there is a well established range of suppliers and agreed standards, could and will be seen as risky, many commentators have highlighted this already during the evolution of FD-SOI.
However FD-SOI, which hopes to service some of the same integrated electronics applications that FinFET transistors are targeting, will be up against some serious challenges long after the technical case is proven. Why? Simply because of the huge sums of hard cash needed to ‘industrialise’ this type of technology.
If you think $half-billion sounds a lot for a pilot line, the actual investment levels needed to progress in this sector are easily comparable to the defence budgets of some of the countries involved, so it should be a very interesting one to watch.